CPU Design using Logic Gates

Let’s embark on an exciting journey to dissect and understand a small, fully functional CPU made entirely of logic gates. This design serves as a proof of concept, illustrating how the main components of a CPU work together to execute a program stored in memory using the Fetch-Decode-Execute cycle.

In this exploration, we will dive deep into the intricacies of a low-spec CPU that, despite its simplicity, encapsulates the fundamental principles of modern computing. Our CPU design includes a clock, a control unit, an ALU, a data store with 4 bytes of data, an instruction store with 8 instructions (each 4 bits long, with 2 bits for the opcode and 2 bits for the operand), and a memory unit acting as RAM or CPU cache, also consisting of 4 bytes of data.

You can access and test our demo CPU by clicking on the following picture:

The logic gates circuits in our CPU contain all the essential components that make up a central processing unit. You can find out more about these essential components using the tab belows:

CPU ClockControl UnitALUAccumulatorData StoreProgram/Instruction StoreMemory UnitMultiplexers
Clock: The heartbeat of our CPU, the clock synchronises all operations, ensuring that each component works in harmony. It generates regular pulses that dictate the timing of the Fetch-Decode-Execute cycle. The clock of the CPU directly controls the Program Counter (PC), an essential register in the FDE cycle to implement sequencing: allowing the CPU to fetch decode and execute one instruction at a time, in sequence.

You can find out more on how to build a program counter using logic gates (and d-type flip-flop circuits)

Note, that in our CPU design we have used a 3-bit program counter, counting from 0 to 7 using the following circuit. The PC will be used by the control Unit to fetch the instruction from the instruction store at the address given by the Program Counter.

Control Unit: The control unit is responsible for directing the operations of all other components within the CPU. It interprets (decodes) the instructions fetched from the instruction store and generates the necessary control signals to execute them. The main logic gates circuit of the control unit is the decoder which decodes the opcode of an instruction. In our CPU, the opcode is made of 2 bits which are used to represent four possible instructions.

You can read more about binary decoder circuits using logic gates.
The table below list the 4 opcodes that our control unit can decode.

Instruction Opcode Mnemonic Purpose
00 HLT Halt the execution of the program. (Note that the provided CPU design also includes a x-HLT switch that bet turned on to ignore/bypass HLT instructions.
01 LDA Use to load a 8-bit value from the data store at a given address (the operand) into the accumulator. e.g. LDA 01 to load the value at address 01 from the data store into the accumulator
10 STA To store the value currently held in the accumulator within the memory unit at a specified address (the operand). e.g. STA 10
11 ADD To add a value from the memory unit at a specified address (the operand) to the accumulator and store the result within the accumulator.
ALU (Arithmetic Logic Unit): Our ALU is designed to perform binary addition on 2 bytes of data. While simple, it demonstrates the core arithmetic operations that are the foundation of more complex computations.
Within the ALU, binary additions are completed using a combination of Half-Adders and Full-Adders logic gates circuits. You can read more about half-adder and full-adder circuits.

Here is a Full-Adder circuit used to add 3 bits together. Click on this circuit to test it.

Note that a more advanced ALU should include other circuits to perform other arithmetic and logic operations such as binary subtractions and binary comparisons.

Accumulator: The accumulator is a special register that temporarily holds data during arithmetic and logical operations. It plays a crucial role in the execution of instructions by storing intermediate results. To temporary store the result of an instruction we are using 8 D-Type flip-flop circuits. The main purpose of a D-Type flip-flop circuit is to store one bit of data. You can read more about D-Type flip-flop circuits.

4-Byte Data Store: This small data store holds the data that the CPU needs to process. It is a simplified version of the registers found in more complex CPUs. Our data store consists of on-off switches which let you change the data being processed by the CPU. An alternative that was used in early computers was to use punched cards to store the data instead of these on-off switches.

Instruction Store: With a capacity of 8 instructions, each 4 bits long, the instruction store holds the program that the CPU will execute. Each instruction consists of an opcode and an operand, which together define the operation to be performed. Our instruction store consists of on-off switches which let you change the instructions being processed by the CPU. Early computers used punched cards instead of these on-off switches.

Note that our CPU uses a different format for the data store (storing data in blocks of 8 bits) and for the instruction store (using 4 bits per instruction), hence the design use two distinct stores for storing the data and the instructions of our program. This means that this CPU differs from the Von Neumann Processor architecture where data and instructions are stored together in primary memory (the memory unit of the CPU or in the RAM). You can read more about the Von Neumann Processor architecture.

4-Byte Memory Unit: Acting as RAM or CPU cache, this memory unit stores data that can be quickly accessed by the CPU. It is an essential component for efficient data retrieval and storage. In this design, the memory unit is part of our CPU and can only store 4 Bytes of data using 4 different memory locations. The MAR and MDR registers are connected to a multiplexer to retrieve the data (Memory Data Register) stored in the memory unit at a specific address (Memory Address Register) In a CPU or within the RAM of a computer system, bits of data are stored using D-Type flip flop circuits.

You can read more on how to design and operate a 4-Byte RAM using logic gates and test the circuit by clicking on the picture below:

Multiplexers: The three set of Multiplexers from our CPU are crucial for fetching data or instructions from the data store, the instruction store, or the memory unit. They act as switches, directing the flow of data within the CPU based on the control signals generated by the control unit. You can read more on how multiplexers are used to fetch data from memory. Here is a multiplexer to retrieve 1 bit of data from four different memory addresses (using a 2-bit address)

Operating the CPU

To operate this CPU you will first need to input your set of instructions (program) and your data in the instruction store and the data store.
Per default the following data is used:

Data Store
Address Binary Value Hexadecimal Value Denary Value
00 00000001 #01 1
01 00000100 #04 4
10 00001010 #0A 10
11 00000000 #00 0

Then you can load your set of instructions (program) in the instruction store. For this demonstration we are using the following program:

Instruction Store
Address Instruction (Binary format) Low Level Instruction Description
0 000 01 00 LDA 00 Load the value at the address 00 from the data store into the accumulator
1 001 10 00 STA 00 Store the accumulator value in the memory unit at the address 00
2 010 01 01 LDA 00 Load the value at the address 01 from the data store into the accumulator
3 011 11 00 ADD 01 Overwrite the accumulator value with the sum of the accumulator and the value in the memory unit at the address 00
4 100 10 01 STA 01 Store the accumulator value in the memory unit at the address 01
5 101 01 10 LDA 10 Load the value at the address 10 from the data store into the accumulator
6 110 11 01 ADD 10 Overwrite the accumulator value with the sum of the accumulator and the value in the memory unit at the address 01
7 111 10 10 STA 10 Store the accumulator value in the memory unit at the address 10

The aim of this program is to calculate the sum of the three numbers stored in the first three addresses of the data store. After completing execution of this program the memory unit should contain:

  • The first value of the data store at address 00: value #01 = 1
  • The sum of the first two values of the data store at address 01: value #01 + #04 = #05 = 5
  • The sum of the first three values of the data store at address 10: value #01 + #04 + #0A = #0F = 15

This should be the state of the memory unit after execution of this program:

Note that as we are not using any HLT instruction, the program will automatically and continuously repeats itself as after reaching value 7, the program counter will reset itself to 0.

You can however stop the program at any time using the on/off switch next to the clock.

As the CPU circuit runs in the web-browser, you will find that its output is unpredictable if you leave or minimise the browser window while it is still running. To avoid this, make sure to stay in the same window while the CPU is running. If needs be, you may need to reload the page at any time to reset the CPU.

Your Turn

The main characteristic of a computer system is that it should be able to run different programs. Your task is to use the switches of both the data store and the instruction store to load your own data and write and test your own computer programs!

Did you like this challenge?

Click on a star to rate it!

Average rating 5 / 5. Vote count: 1

No votes so far! Be the first to rate this post.

As you found this challenge interesting...

Follow us on social media!