In our previous blog posts we have looked at a few logic gates circuits used inside a CPU to perform binary additions (Half adders and full adders) and to retain a bit of information using a D-Type flip-flop circuit (Data Cell).
By studying assembly language (using the LMC simulator) we have aslo investigated how the CPU uses the FDE cycle to fetch an instruction, decode it and execute it.
The purpose of this blog post is to investigate how the CPU can fetch data (data or instructions) from memory as this is an essential part of the FDE cycle.
A multiplexer is a logic gates circuit used to fetch a bit of data from memory at a given memory address. A processor has several multiplexers (MUX) controlling the data and address buses. Multiplexers are switches allowing the processor to select data from multiple data sources. To select which data source should be used a multiplexer has one or more control lines (a.ka. Selectors). The output of a multiplexer is the selected data.
Let’s investiagte a basic multiplexer used to select data from two data cells. With only two data cells (A and B) you only need 1 bit to code their address:
- Address 0 = Input A
- Address 1 = Input B
The Truth Table of this 2-input Multiplexer is:
By combining two of these multiplexers together we can select between 4 inputs, A, B, C and D.
In this multiplexer we have two selectors: S1, S2 to get the following outputs from the 4 memory addresses: 00,10,01 and 11:
This is how our 4-input multiplexer behaves:
By combining more of these multiplexers together we can fetch data from 4-bit memory locations or 8-bit memory locations and so on.
- With 1 multiplexer (2 inputs, 1 selector) we can fetch data from 2 memory locations.
- With 2 multiplexers (4 inputs, 2 selectors) we can fetch data from 4 memory locations.
- With 3 multiplexers (8 inputs, 3 selectors) we can fetch data from 8 memory locations.
- With 4 multiplexers (16 inputs, 4 selectors) we can fetch data from 16 memory locations.
- With N multiplexers (2N inputs, N selectors) we can fetch data from 2N memory locations.
From bits to Bytes
Previously, (see blog post) we have seen that a data cell consists of a D-Type flip-flop logic gates circuit and holds one bit of data.
In the CPU, registers, Level 1 cache and in he RAM, memory units use such data cells.
By lining up 8 data cells in parallel, we can then store 1 Byte (8-bits) of data.
To retrieve the content of an 8-bit memory unit, we can connect 8 multiplexers in parallel.
Address Bus & Data Bus
The “wires” between the multiplexers and the data cells are called buses. In an 8-bit processor each bus consists of 8 wires in parallel.
The buses that connect the inputs (e.g. A,B,C,D in the diagram above) are called data buses as they carry the actual data to be fetched.
The buses that connect the selectors (e.g. S1 and S2) are called address buses as they carry the address of where the data is to be fetched from. The more wires in the address bus, the more memory locations can be reached (2N), so:
- For an address bus of 8 wires you can reach 256 memory locations,
- with 16 wires (2-Byte addresses) you can reach over 64,000 memory locations,
- with 32 wires (4-Byte addresses) you can reach over 4,000,000,000 memory locations. (e.g. 4GB RAM)
Data or Instructions?
Through the FDE cycle, the CPU has to fetch instructions (lines of machine code to execute) as well as data (e.g. oerands). In a Von Neumann processor architecture, both instructions and data are stored in the same locations using the same format. The same multiplexers can hence be used to fetch either data or instructions.