# 4-bit counter using D-Type flip-flop circuits

In this blog post we will design an electronic circuit using logics gates (combined into D-Type flip-flop circuits) to create a 4-bit binary counter. This approach will help us understand how a program counter may be designed within the CPU and automatically incremented for each tick of the clock cycle.

#### D-Type Flip-Flop Circuits?

A D-Type Flip-Flop circuit is built using four NAND logic gates connected as follows:

We represent a D-Type Flip-Flop Circuit as follows. You can change the input values D and E by clicking on the corresponding buttons below to see the impact on the outputs Q and Q.

A D-Type Flip-Flop Circuit can be used to store 1 bit of information. It has two input pins (Called D (Data) and E (Enabler) and two output pins (Q and Q = NOT Q).

You can read more about how Random Memory is designed using D-Type flip flop circuits.

The truth table of a D-Type Flip-Flop circuit is as follows:

When the enabler input E is set to 1, the output Q can be set to the Data input D.
When the enabler input E is set to 0, the output Q cannot be changed. It remains as its previous value. In other word it retains its value. This is why this circuit is used to create memory cells (e.g in the RAM).

You can test this circuit online by clicking on the picture below:

#### Frequency Division

Another use of a D-Type flip-flop circuit is to perform a frequency division of a signal. For this type of circuit, we will need to use a slight variation to our D-Type Flip Flop by using an edge triggered D-type flip flop. The difference being that the output Q and Q can only change state with the transition of the clock pulse, which means when the Enabler is changing state from 0 to 1. After that, when the enabler is set to 1, the outputs Q and Q remain the same even when the data input D changes.

You can test this circuit online by clicking on the picture below:

By creating a feedback loop (connecting the output Q to the Data pin, D) and applying a regular clock signal to the Enabler pin (E), the resulting signal (pin Q) has the frequency of the input signal divided by two.

This diagram represents both the input and output signals when a feedback loop is applied to a D-Type flip-flop circuit:

You can test this frequency divider circuit by clicking on the picture below:

#### Designing a 4-bit binary counter

By applying the same circuit in series we can then divide the frequency by 2, 4 and 8. The original signal (clock) and the 3 resulting signals will then produce the desired counting effect:

You can test this circuit with our logic gates circuit simulator by clicking on the picture below:

And here is the full circuit using Logic.ly:

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