The Von Neumann Processor Architecture

John Von Neumann (1903-1957) was a Hungarian-American mathematician, physicist and computer scientist and a founding figure in computer science, with significant contributions to computing hardware design.

The Von Neumann architecture refers to a processor architecture which has access to a program stored in primary memory as a set of instructions. A processor based on the Von Neumann architecture can execute these instructions sequentially using the Fetch Decode and Execute cycle (FDE Cycle).

Nowadays most general purpose computers are still relying on the key characteristics of this architecture. Within the Von Neumann architecture the processor consists of a control unit, an arithmetic logic unit (ALU) and some key registers used to store numerical values within the processor. These include a Program Counter (PC), an Accumulator, a Current Instruction Register (CIR), a Memory Data Register (MDR) and a Memory Address Register (MAR). These registers are used during the FDE cycle for the processor to fetch instructions and transfer data (between the processor and primary memory) and to execute these instructions.

The rate at which a processor can perform the FDE cycles to process instructions is called the clock speed. For instance, a processing unit with a 3.5GHz clock speed can process 3,500,000,000 instructions per second.

Recent computers have a high clock speed and more advanced processors may also have multiple cores (dual core, quad core etc.) which enable them to process several FDE cycles simultaneously. They may also contain cache within the CPU which can be used to store (and retrieve at a very fast rate) recently or frequently used instructions or data without the need to retrieve these from primary memory. A Central Processing Unit (CPU) with multiple cores, a certain amount of cache and a high clock speed will benefit from an increased performance.


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