In this post we will create an **Arithmetic & Logic Unit (ALU)** using logic gates. The ALU is one of the main component of the CPU. It is used in the Execution stage of the FDE cycle to perform all the logical (e.g. AND, OR, NOT) operations and all the arithmetic calculations (e.g. ADD, SUB instructions).

Our ALU will perform 4 different operations: three **logical operations** (NOT, OR and AND) and one **arithmetical operation** (ADD: +). Here is the instruction table for our ALU:

The ALU will have a built-in 2-to-4 binary decoder that can decode 2-bit instructions represented by inputs F_{0}F_{1}.

The **Logic unit** of our ALU will apply a NOT mask to input A or an OR and an AND masks to inputs A and B.

The **Arithmetic unit** will use a full adder to perform an addition of A and B (including carried values) and output the binary sum and the carry out value.

#### 1-bit Arithmetic & Logic Unit

Here is the logic gates diagram for out 1-bit ALU:

#### 8-bit Arithmetic & Logic Unit

Let’s represent our 1-bit ALU with the following diagram:

By connecting eight 1-bit ALU together, we obtain an 8-bit ALU:

Note that a single decoder can be used to control all the 1-bit ALUs. There is no need to replicate this decoder eight times.

The last carried value can be used to detect overflows when performing a binary addition on the two Bytes of data A and B.