A decoder is a logic circuit that converts a coded input to a “decoded” output by converting the input into a different format. Binary decoders can be used to:
- Convert BCD/binary value into “denary format”, “octal format” or “hexadecimal format”,
- Decoding the opcode of an instruction (Decode stage of the FDE Cycle).
One of the key characteristics of a decoder is the number of inputs and the outputs of its logic circuit. Generally the input code has fewer bits than output code. In this blog post we will investigate the most commonly used binary decoders: 2-to-4 decoder, 3-to-8 decoder and 4-to-16 decoder.
2-to-4 Binary Decoder
A 2-to-4 binary decoder has 2 inputs and 4 outputs. It can be used to convert any 2-bit binary number (0 to 3) into “denary” using the following truth table:
3-to-8 Binary Decoder
A 3-to-8 binary decoder has 3 inputs and 8 outputs. Its logic gate diagram is very similar to the 2-to-4 logic gates diagram, combining a few extra NOT and AND gates to generate the 8 required outputs. It can be used to convert any 3-bit binary number (0 to 7) into “octal” using the following truth table:
Logic Gates Diagram:
4-to-16 Binary Decoder
A 4-to-16 binary decoder has 4 inputs and 8 outputs. It can easily be created by combining two 3-to-8 decoders together and can be used to convert any 4-bit binary number (0 to 15) into “hexadecimal” using the following truth table.
Note that a 4-to-16 Decoder can be used as an instruction decoder to decode 4-bits opcodes from a recently fetched instruction. Each output pin corresponding on one of the low level instruction (e.g. in LMC: LDA, STA, ADD, SUB, BRP, BRZ, BRA, HLT etc…). This is how the decode stage of the FDE cycle is implemented using logic gates!
Whereas binary decoders are used to implement the Decode stage of the FDE cyle, the Fetch stage is implemented using Multiplexers.